I. Field of the Invention
The present invention relates to electronic systems having circuit boards installed therein and, more particularly, to a system and method for allowing live insertion of the circuit boards into the system by regulating staggered connection insertion timing of the boards.
II. Background and Prior Art
Given the increasing reliance on enterprise networking and online processing reliance, customers today are demanding maximum availability of electronic processing systems. It is therefore imperative that these electronic processing systems have as little "downtime", or time when the system is inoperable, as possible. The importance of minimum downtime is shown by the increasing popularity and demand of fault-tolerant systems, which are specifically designed to tolerate faults in the system (and even, in some cases, to detect and to correct its own faults) without having an outage.
However, the vast majority of system downtime (typically, from 70-90%) is not due to the whole system going down or "crashing" but rather is due to planned outages, or downtime which has been previously planned for problem diagnosis, part replacement, hardware reconfiguration and the like. Many times, a single adapter module (sometimes called "a card" or "a board") needs to be repaired or replaced for upgrade while the remainder of the system is operating properly. Shutting down an entire system for such routine service can impact a large number of users needlessly.
The preferred method of repairing or replacing a single module in a system is by live insertion/removal, or "hot-swapping", where the particular module is removed while the system remains powered up and otherwise functioning properly. Dynamic insertion and removal of adapter modules, if achieved non-disruptively, can allow major gains in overall system availability. Service diagnosis, corrective actions, and hardware reconfiguration can be performed seamlessly and in realtime.
In order to have live insertion/removal, the adapter modules and/or the system need to have specific circuitry or software for providing the live insertion/removal capability. When an unpowered module, without such capability, is inserted into a live, or powered, system, its insertion may cause voltage spikes to appear on data lines interconnected throughout the system. This is the result of the module's components receiving the power from the system and charging up for operation. These momentary spikes, or transients, can cause disruption of communications by corrupting the data flow between parties in the system. This disruption may be especially troublesome where there are many users in the system which are interconnected and communicating via an active bus.
There have been many attempts at providing reliable live insertion/removal capability. For instance, some systems use "umbilical cords" (or "cheater cords"), or cables providing power, attached to the modules to be inserted. The umbilical cords provide the necessary power to the module prior to the module's insertion and the module is allowed time to charge so that, when it is inserted, its components (or the "module load") have pre-charged and will not cause a spike to be transmitted on the system data lines. The problem is that this method of live insertion/removal is expensive given the cabling requirements, especially in high connectivity environments where a large number of high frequency cabling, such as coaxial cabling, is used. Further, the extra umbilical cabling is not user friendly as it is difficult and must be handled carefully due to safety concerns as the cord is powered.
A commonly assigned patent application, G. Hahn et al., "A Hot Pluggable Electrical Circuit", U.S. patent application Ser. No 08/003,074, filed Jan. 11, 1993 now pending, describes a circuit for minimizing the electrical transients resulting from insertion of an electrical circuit into a non-quiesced signal net by preconditioning signal net stub parasitics on the circuit being dynamically live inserted. However, this implementation must be such that stable pre-charge can be guaranteed before the inserted feature contacts the live parallel bus. This entails the completion of power-up, voltage stabilization, and time to fully charge stub parasitics. If enough time is not allowed so that stable pre-charge can be assured, then feature insertion will likely corrupt the information being transferred between parties on an active parallel bus.
Other systems provide a current-limiting circuit on the module, through which the module load is initially charged before supplying the module load with power directly. This is implemented, for example, using field-effect transistors (FETs) such as metal oxide semiconductor (MOS) FETs, in conjunction with "sequential" connectors. A sequential connector is one in which certain pins of the connector are staggered with respect to the remainder of the pins so as to make or break an electrical connection before other pins of the connector. Normally, in such systems, the connection sequence is such that the first to connect is the module ground and the board ground, then to connect the board voltage supply to the current limiter on the module, and finally to connect the voltage supply to the module load directly.
While such systems are capable of providing live insertion, several problems remain. First, there is the obvious expense of providing a separate current-limiting circuit on each module which may plug into a system. Second, such systems are susceptible to high-frequency noise resulting from parasitic oscillations occurring when the drain pin of the system is joined to the module. This connection typically produces an inrush of current into the card to charge the MOSFET's parametric capacitance, typically about 3,000 pF.
Some of these problems are solved by a system described another commonly assigned patent application, P. Bellamy et al., "Sequential Connector", Ser. No. 07/661,283 now U.S. Pat. No. 5,268,592. In this system, staggered connections are used to enable a current limiting power MOSFET so that the module's power supply is slowly charged up. As in other staggered connection systems, the P. Bellamy et al. connector provides some pins on either the module connector or on its mating system connector which are slightly longer than others so that the longer ones make initial contact. This allows the electrical signals conveyed by the longer pins to flow between the module and the system before those conveyed by the shorter ones.
The problem is that the amount of time between the initial contact of the longer pins (and thus initial current flow) and the subsequent contact of the shorter pins (and subsequent current flow) is a short period time--as an installer is moving the module with sufficient force and speed so that its connector may become properly seated with the mating connector. Thus, the time allowed for load pre-charge is merely the amount of time it takes the connector to sweep across the long pins prior to contacting the shorter pins. This amount of time may or may not be sufficient for the load pre-charge.
An additional problem is that this amount of time will vary from installer to installer as each installer may install a module differently than the next installer. As a module normally slides freely on guiding tracks or rails within a system, the insertion speed of the module is not inhibited in any way with the exception of the insertion force required by the module and system connectors. This force is easily overcome by an installer so that race conditions result in that there is a race between the load pre-charge and voltage stabilization and the engagement of the shorter pins. There is no practical way of controlling the time, or guaranteeing a consistently minimum time, between the initial contact of the longer pins and the subsequent contact of the shorter pins as each installer will perform the same function in a different manner causing different results.
If not enough time is provided between the initial contact of the longer pins and the subsequent contact of the shorter pins, communication disruption will occur--especially where the insertion is into an active parallel bus as transients will corrupt data flowing between parties in the system.